The present invention is directed to communication systems and methods thereof.
Over the past few decades, computer processors have become faster and faster, loosely following Moore's law, which states that the number of transistors in a densely integrated circuit has doubled approximately every two years. As processors become faster in processing data, data buses that connect processors to other components (e.g., memory, I/O, graphics) of computer systems need to provide high-speed and large bandwidth communication links. Physical distance between a central processing unit (CPU) and the DRAM is often very short and often measured in centimeters, but the amount of data transfers between the two entities can be large over a short amount of time. For example, when CPU operating at 2 GHz with multiple cores, a large amount of data is often moved between CPU and DRAM through a memory bus at a high speed (measured in Gbps). Typically, parallel communication protocols are used for this type of high-speed data communication. Unfortunately, performance and data rate are limited by, among other things, channel loss and intersymbol interference (ISI), which are characteristics of the communication channel. Decision feedback equalizer (DFE), which is usually implemented at the receiver, is often used to improve performance of data communication by reducing or eliminating the effects of channel loss and ISI.
Over the past, there have been various conventional DFE implementations for reducing or removing inter-symbol interference. Unfortunately, they have been inadequate for various reasons. Therefore, improved systems and methods are desired.